Date of Award

5-9-2015

Degree Type

Thesis

Degree Name

Master of Science (MS)

Department

Computer Science

First Advisor

Sushil K. Prasad

Second Advisor

Xiaojun Cao

Third Advisor

Yanqing Zhang

Abstract

This thesis is devoted to the investigation of prioritization mechanism for web based anomaly detection. We propose a hardware realization of parallel binary heap as an application of web based anomaly prioritization. The heap is implemented in pipelined fashion in FPGA platform. The propose design takes O(1) time for all operations by ensuring minimum waiting time between two consecutive operations. We present the various design issues and hardware complexity. We explicitly analyze the design trade-offs of the proposed priority queue implementations.

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