Date of Award
12-4-2006
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Computer Science
First Advisor
A. P. Preethy - Chair
Second Advisor
Michael Weeks
Third Advisor
Saeid Belkasim
Abstract
ABSTRACT Due to the rapid progress in the field of VLSI, improvements in speed, power and area are quite evident. Research and development in this field are motivated by growing markets of portable mobile devices such as personal multimedia players, cellular phones, digital camcorders and digital cameras. Among the recently popular logic families, pass transistor logic is promising for low power applications as compared to conventional static CMOS because of lower transistor count. This thesis proposes four novel designs for Booth encoder and selector logic using pass logic principles. These new designs are implemented and used to build a 64 x 64-bit multiplier. The proposed Booth encoder and selector logic are competitive with the existing and shows substantial reduction in transistor count. It also shows improvements in delay when compared to two of the three published works.
DOI
https://doi.org/10.57709/1059376
Recommended Citation
Thankachan, Shibi, "64 x 64 Bit Multiplier Using Pass Logic." Thesis, Georgia State University, 2006.
doi: https://doi.org/10.57709/1059376